1. Field of the Invention
The present invention is directed to synchronizing video and graphics images displayed on multiple display devices.
2. Related Art
Obtaining visual realism is crucial in computer graphics systems. To this end, it is often necessary to use multiple video or graphics processors to produce multiple levels of images on a single display device (e.g., a CRT, LCD, active matrix or plasma display). In the alternative, some video or graphics systems seek to achieve visual reality by generating a large visual image across multiple display devices. Each processor contributes to the overall image by providing a video or graphics signal representing, for example, either a front, left, or right view of the scene being displayed. Proper synchronization between the signals being provided to the various display devices is key to maintaining the reality of the scene being presented.
Several standards have been established that define various formats for video signals. The National Television Standards Committee (NTSC), Phase Alternate Line (PAL), and SEquential Couleur Avec Memoire (SECAM) are three widely accepted formats for television signals. Similarly, standards such as Video Graphics Array (VGA) and Monochrome Display Adaptor (MDA) are used to define display formats for computer displays. Depending on the standard used, a particular number of pixels, for example, 720, will be used to define a display or scan line. The scan lines are separated by synchronization pulses.
Horizontal synchronization (H-sync) pulses and Vertical synchronization (V-sync) pulses are two key components of the signals that are used to provide synchronization between multiple displays. These pulses represent the beginning of a new scan line in either the horizontal or vertical direction. When the horizontal or vertical synchronization pulses of the video signals generated by the participating processors are not aligned, visible distortions will be apparent.
Phase-locked loop (PLL) techniques are used to provide horizontal synchronization between multiple displays. Generally, these techniques phase-lock the horizontal synchronization pulse from a slave processor to the horizontal synchronization pulse of a master processor. A drawback to using a conventional phase-locked loop, however, is that the loop speed is fixed. A slow loop will be slow to adapt when the signals get out of synchronization. In contrast, a very fast loop will snap the signals into synchronization, often causing visible distortions or jitter in the display.
Vertical synchronization is usually achieved by resetting the vertical position of the slave processor upon the occurrence of a vertical reset in the master processor. In this way, vertical synchronization is achieved immediately. This process of “snapping” or causing the processors to become immediately synchronized with respect to their vertical positions also results in visible distortions.
Synchronization is made more difficult by the varying complexities of the images being presented on the various displays. As a result, many graphics systems will become desynchronized and/or produce visual artifacts or distortions in the resulting image. What is needed is a solution that will provide for vertical and horizontal synchronization of multiple displays while avoiding visual distortions.